565 lines
19 KiB
C
565 lines
19 KiB
C
/**
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* Copyright (c) 2022, Nations Technologies Inc.
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*
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* All rights reserved.
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*
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* This software is the exclusive property of Nations Technologies Inc. (Hereinafter
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* referred to as NATIONS). This software, and the product of NATIONS described herein
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* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties
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* of the People’s Republic of China and other applicable jurisdictions worldwide.
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*
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* NATIONS does not grant any license under its patents, copyrights, trademarks, or other
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* intellectual property rights. Names and brands of third party may be mentioned or referred
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* thereto (if any) for identification purposes only.
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*
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* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and
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* improvements to this software at any time without notice. Please contact NATIONS and obtain
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* the latest version of this software before placing orders.
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* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes
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* no responsibility for the accuracy and reliability of this software.
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*
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* It is the responsibility of the user of this software to properly design, program, and test
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* the functionality and safety of any application made of this information and any resulting product.
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* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or
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* consequential damages arising in any way out of the use of this software or the Product.
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*
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* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any
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* malfunction or failure of which may cause loss of human life, bodily injury or severe property
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* damage. Such applications are deemed, “Insecure Usage”.
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*
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* All Insecure Usage shall be made at user’s risk. User shall indemnify NATIONS and hold NATIONS
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* harmless from and against all claims, costs, damages, and other liabilities, arising from or related
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* to any customer’s Insecure Usage.
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* Any express or implied warranty with regard to this software or the Product, including,but not
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* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement
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* are disclaimed to the fullest extent permitted by law.
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* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe
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* or otherwise distribute this software for any purposes, in whole or in part.
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*
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* NATIONS products and technologies shall not be used for or incorporated into any products or systems
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* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations.
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* User shall comply with any applicable export control laws and regulations promulgated and administered by
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* the governments of any countries asserting jurisdiction over the parties or transactions.
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**/
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/**
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*\*\file system_n32g430.c
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*\*\author Nations
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*\*\version v1.0.3
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*\*\copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
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*/
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#include "n32g430.h"
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/* Uncomment the line corresponding to the desired System clock (SYSCLK)
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frequency (after reset the HSI is used as SYSCLK source)
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IMPORTANT NOTE:
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==============
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1. After each device reset the HSI is used as System clock source.
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2. Please make sure that the selected System clock doesn't exceed your
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device's maximum frequency.
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3. If none of the define below is enabled, the HSI is used as System clock
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source.
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4. The System clock configuration functions provided within this file assume
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that:
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- For Low, Medium and High density Value line devices an external 8MHz
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crystal is used to drive the System clock.
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- For Low, Medium and High density devices an external 8MHz crystal is
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used to drive the System clock.
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- For Connectivity line devices an external 25MHz crystal is used to
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drive the System clock. If you are using different crystal you have to adapt
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those functions accordingly.
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*/
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#define SYSCLK_USE_HSI 0
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#define SYSCLK_USE_HSE 1
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#define SYSCLK_USE_HSI_PLL 2
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#define SYSCLK_USE_HSE_PLL 3
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#ifndef SYSCLK_FREQ
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#define SYSCLK_FREQ 128000000
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#endif
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#ifndef SYSCLK_SRC
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#define SYSCLK_SRC SYSCLK_USE_HSE_PLL
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#endif
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#if SYSCLK_SRC == SYSCLK_USE_HSI
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#if SYSCLK_FREQ != HSI_VALUE
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#error SYSCL_FREQ must be set to HSI_VALUE
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#endif
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#elif SYSCLK_SRC == SYSCLK_USE_HSE
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#ifndef HSE_VALUE
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#error HSE_VALUE must be defined!
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#endif
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#if SYSCLK_FREQ != HSE_VALUE
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#error SYSCL_FREQ must be set to HSE_VALUE
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#endif
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#elif SYSCLK_SRC == SYSCLK_USE_HSI_PLL
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#if SYSCLK_FREQ < 32000000
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#error When SYSCLK_SRC is PLL, SYSCLK_FREQ must be greater than or equal to 32MHz
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#endif
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#if (SYSCLK_FREQ % (HSI_VALUE / 2) == 0) && (SYSCLK_FREQ / (HSI_VALUE / 2) >= 2) \
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&& (SYSCLK_FREQ / (HSI_VALUE / 2) <= 32)
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#define PLLSRC_DIV 2
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#define PLL_MUL (SYSCLK_FREQ / (HSI_VALUE / 2))
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#elif (SYSCLK_FREQ % HSI_VALUE == 0) && (SYSCLK_FREQ / HSI_VALUE >= 2)
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&& (SYSCLK_FREQ / HSI_VALUE <= 32)
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#define PLLSRC_DIV 1
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#define PLL_MUL (SYSCLK_FREQ / HSI_VALUE)
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#else
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#error Cannot make a PLL multiply factor to SYSCLK_FREQ.
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#endif
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#elif SYSCLK_SRC == SYSCLK_USE_HSE_PLL
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#if SYSCLK_FREQ < 32000000
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#error When SYSCLK_SRC is PLL, SYSCLK_FREQ must be greater than or equal to 32MHz
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#endif
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#ifndef HSE_VALUE
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#error HSE_VALUE must be defined!
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#endif
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#if ((SYSCLK_FREQ % (HSE_VALUE / 2)) == 0) && (SYSCLK_FREQ / (HSE_VALUE / 2) >= 2) \
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&& (SYSCLK_FREQ / (HSE_VALUE / 2) <= 32)
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#define PLLSRC_DIV 2
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#define PLL_MUL (SYSCLK_FREQ / (HSE_VALUE / 2))
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#elif (SYSCLK_FREQ % HSE_VALUE == 0) && (SYSCLK_FREQ / HSE_VALUE >= 2)
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&& (SYSCLK_FREQ / HSE_VALUE <= 32)
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#define PLLSRC_DIV 1
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#define PLL_MUL (SYSCLK_FREQ / HSE_VALUE)
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#else
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#error Cannot make a PLL multiply factor to SYSCLK_FREQ.
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#endif
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#else
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#error wrong value for SYSCLK_SRC
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#endif
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/* If you want to use VECT_TAB_SRAM, release the comment*/
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/* #define VECT_TAB_SRAM */
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/* Vector Table base offset field. This value must be a multiple of 0x200. */
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#define VECT_TAB_OFFSET 0x0
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/** Clock Definitions **/
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/* System Clock Frequency (Core Clock) */
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uint32_t SystemClockFrequency = SYSCLK_FREQ;
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const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
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static void System_Clock_Set(void);
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#ifdef DATA_IN_ExtSRAM
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static void SystemInit_ExtMemCtl(void);
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#endif /* DATA_IN_ExtSRAM */
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typedef void (*pFunction)(uint32_t, uint32_t*);
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/**
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*\*\name PLL_TrimValueLoad.
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*\*\fun Load PLL trim value.
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*\*\param none
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*\*\return none
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**/
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void PLL_TrimValueLoad(void)
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{
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pFunction get_nvr = (pFunction)(0x1FFF02A5);
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uint32_t value = 0, value1,value3,value4;
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uint32_t temp = 0;
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/* Disable the iCache */
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FLASH->AC &= FLASH_ICACHE_DIS;
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/* ICache Reset */
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FLASH->AC |= FLASH_ICAHRST_MSK;
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get_nvr(0x1FFFF020, &value);
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if((value & 0xFF) <= 5)
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{
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get_nvr(0x1FFFF230,&value);
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/* Big-endian little-endian exchange */
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value1 = value >>24;
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value3 = (value & 0xFF0000)>>8;
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value4 = (value & 0xFF00)<<8;
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value = value1 | value3 | value4;
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temp = AFEC->TRIMR1 &0xFF000000;
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temp |= value;
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AFEC->TRIMR1 = temp;
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}
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else
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{
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}
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/* Enable the iCache */
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FLASH->AC |= FLASH_ICACHE_EN;
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}
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/**
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*\*\name System_Initializes.
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*\*\fun Setup the microcontroller system
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*\*\ Initialize the Embedded Flash Interface, the PLL and update the
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*\*\ SystemClockFrequency variable.
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*\*\param none.
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*\*\return none
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*\*\note This function should be used only after reset.
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**/
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void System_Initializes(void)
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{
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/* FPU settings */
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#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
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/* set CP10 and CP11 Full Access */
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SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2));
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#endif
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/* Reset the RCC clock configuration to the default reset state(for debug purpose) */
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/* Set HSIEN bit */
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RCC->CTRL |= RCC_CTRL_HSIEN;
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/* Reset SCLKSW, AHBPRES, APB1PRES, APB2PRES and MCO bits */
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RCC->CFG &= ~(RCC_CFG_SCLKSW|RCC_CFG_AHBPRES|RCC_CFG_APB1PRES|RCC_CFG_APB2PRES|RCC_CFG_MCO);
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/* Reset HSEEN, CLKSSEN and PLLEN bits */
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RCC->CTRL &= ~(RCC_CTRL_HSEEN|RCC_CTRL_CLKSSEN|RCC_CTRL_PLLEN);
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/* Reset HSEBP bit */
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RCC->CTRL &= ~RCC_CTRL_HSEBP;
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/* Reset PLLSRC, PLLHSEPRES, PLLMULFCT bits */
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RCC->CFG &= ~(RCC_CFG_PLLSRC|RCC_CFG_PLLHSEPRES|RCC_CFG_PLLMULFCT);
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/* Reset CFG2 register */
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RCC->CFG2 = RCC_CFG2_ADC1MPRES_DIV8;
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/* Reset PLLHSIPRE register */
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RCC->PLLHSIPRE |= RCC_PLLHSIPRE_PLLHSIPRE;
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/* Disable all interrupts and clear pending bits */
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RCC->CLKINT = (RCC_CLKINT_LSIRDICLR|RCC_CLKINT_LSERDICLR|RCC_CLKINT_HSIRDICLR
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|RCC_CLKINT_HSERDICLR|RCC_CLKINT_PLLRDICLR
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|RCC_CLKINT_CLKSSICLR|RCC_CLKINT_LSESSICLR);
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RCC->APB1PCLKEN |= RCC_APB1PCLKEN_PWREN;
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RCC->APB1PCLKEN &= (uint32_t)(~RCC_APB1PCLKEN_PWREN);
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/* Enable ICACHE and Disable Prefetch Buffer */
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FLASH->AC |= (uint32_t)(FLASH_AC_ICAHEN);
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FLASH->AC &= (~((uint32_t)FLASH_AC_PRFTBFEN));
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#ifdef DATA_IN_ExtSRAM
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SystemInit_ExtMemCtl();
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#endif /* DATA_IN_ExtSRAM */
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/* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
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/* Configure the Flash Latency cycles and enable prefetch buffer */
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System_Clock_Set();
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#ifdef VECT_TAB_SRAM
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SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
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#else
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SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
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#endif
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}
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/**
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*\*\name System_Clock_Frequency_Update.
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*\*\fun Update SystemClockFrequency variable according to Clock Register Values.
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*\*\ The SystemClockFrequency variable contains the core clock (HCLK), it can
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*\*\ be used by the user application to setup the SysTick timer or
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*\*\ configure other parameters.
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*\*\param none.
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*\*\return none
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*\*\note Each time the core clock (HCLK) changes, this function must be called
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*\*\ to update SystemClockFrequency variable value. Otherwise, any
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*\*\ configuration based on this variable will be incorrect.
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*\*\
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*\*\note The system frequency computed by this function is not the real
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*\*\ frequency in the chip. It is calculated based on the predefined
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*\*\ constant and the selected clock source:
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*\*\
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*\*\ - If SYSCLK source is HSI, SystemClockFrequency will contain the HSI_VALUE
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*\*\
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*\*\ - If SYSCLK source is HSE, SystemClockFrequency will contain the HSE_VALUE
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*\*\
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*\*\ - If SYSCLK source is PLL, SystemClockFrequency will contain the
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*\*\ HSE_VALUE or HSI_VALUE multiplied by the PLL factors.
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*\*\
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*\*\ HSI_VALUE is a constant defined in n32g430.h file (default value
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*\*\ 8 MHz) but the real value may vary depending on the variations
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*\*\ in voltage and temperature.
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*\*\
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*\*\ HSE_VALUE is a constant defined in N32G430.h file (default value
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*\*\ 8 MHz, depedning on the product used), user has to ensure
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*\*\ that HSE_VALUE is same as the real frequency of the crystal used.
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*\*\ Otherwise, this function may have wrong result.
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*\*\
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*\*\ - The result of this function could be not correct when using
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*\*\ fractional value for HSE crystal.
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**/
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void System_Clock_Frequency_Update(void)
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{
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uint32_t temp_value = SYSCLOCK_SRC_HSI;
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uint32_t pllmull_value = 0, pllsource_value = 0;
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/* Get SYSCLK source
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* -------------------------------------------------------*/
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temp_value = RCC->CFG & RCC_CFG_SCLKSTS;
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switch (temp_value)
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{
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case SYSCLOCK_SRC_HSI: /* HSI used as system clock */
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SystemClockFrequency = HSI_VALUE;
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break;
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case SYSCLOCK_SRC_HSE: /* HSE used as system clock */
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SystemClockFrequency = HSE_VALUE;
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break;
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case SYSCLOCK_SRC_PLL: /* PLL used as system clock */
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/* Get PLL clock source and multiplication factor
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* ----------------------*/
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pllmull_value = RCC->CFG & RCC_CFG_PLLMULFCT;
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pllsource_value = RCC->CFG & RCC_CFG_PLLSRC;
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if ((pllmull_value & RCC_CFG_PLLMULFCT_4) == 0)
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{
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// PLLMULFCT[4] = 0
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pllmull_value = (pllmull_value >> 18) + 2;
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}
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else
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{
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// PLLMULFCT[4] = 1
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pllmull_value = ((pllmull_value >> 18) - 496) + 1;
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}
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if (pllsource_value == 0x00)
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{
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/* HSI selected as PLL clock entry */
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if ((RCC->PLLHSIPRE & RCC_PLLHSIPRE_PLLHSIPRE) != (uint32_t)RESET)
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{ /* HSI oscillator clock divided by 2 */
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SystemClockFrequency = (HSI_VALUE >> 1) * pllmull_value;
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}
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else
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{
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SystemClockFrequency = HSI_VALUE * pllmull_value;
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}
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}
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else
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{
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/* HSE selected as PLL clock entry */
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if ((RCC->CFG & RCC_CFG_PLLHSEPRES) != (uint32_t)RESET)
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{ /* HSE oscillator clock divided by 2 */
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SystemClockFrequency = (HSE_VALUE >> 1) * pllmull_value;
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}
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else
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{
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SystemClockFrequency = HSE_VALUE * pllmull_value;
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}
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}
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break;
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default:
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SystemClockFrequency = HSI_VALUE;
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break;
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}
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/* Compute HCLK clock frequency ----------------*/
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/* Get HCLK prescaler */
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temp_value = AHBPrescTable[((RCC->CFG & RCC_CFG_AHBPRES) >> 4)];
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/* HCLK clock frequency */
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SystemClockFrequency >>= temp_value;
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}
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/**
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*\*\name System_Clock_Set.
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*\*\fun Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
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*\*\param none.
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*\*\return none
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**/
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static void System_Clock_Set(void)
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{
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volatile uint32_t temp_value,temp_value1 = 0;
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volatile bool status_value = 0;
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volatile uint32_t counter_value = 0;
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uint8_t id_version = 0;
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#if ((SYSCLK_SRC == SYSCLK_USE_HSI) || (SYSCLK_SRC == SYSCLK_USE_HSI_PLL))
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/* Enable HSI */
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RCC->CTRL |= ((uint32_t)RCC_CTRL_HSIEN);
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/* Wait till HSI is ready and if Time out is reached exit */
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do
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{
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status_value = RCC->CTRL & RCC_CTRL_HSIRDF;
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counter_value++;
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} while ((status_value == 0) && (counter_value != HSI_STARTUP_TIMEOUT));
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status_value = ((RCC->CTRL & RCC_CTRL_HSIRDF) != RESET);
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if (!status_value)
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{
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/* If HSI fails to start-up, the application will have wrong clock
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* configuration. User can add here some code to deal with this error */
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SystemClockFrequency = HSI_VALUE;
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return;
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}
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#elif SYSCLK_SRC == SYSCLK_USE_HSE || SYSCLK_SRC == SYSCLK_USE_HSE_PLL
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/* Enable HSE */
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RCC->CTRL |= ((uint32_t)RCC_CTRL_HSEEN);
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/* Wait till HSE is ready and if Time out is reached exit */
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do
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{
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status_value = RCC->CTRL & RCC_CTRL_HSERDF;
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counter_value++;
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} while ((status_value == 0) && (counter_value != HSE_STARTUP_TIMEOUT));
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status_value = ((RCC->CTRL & RCC_CTRL_HSERDF) != RESET);
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if (!status_value)
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{
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/* If HSE fails to start-up, the application will have wrong clock
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* configuration. User can add here some code to deal with this error */
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SystemClockFrequency = HSI_VALUE;
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return;
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}
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#endif
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/* Flash wait state
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C version D version
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0: HCLK <= 32M 0: HCLK <= 39M
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1: HCLK <= 64M 1: HCLK <= 78M
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2: HCLK <= 96M 2: HCLK <= 117M
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3: HCLK <= 128M 3: HCLK <= 128M
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*/
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FLASH->AC &= (uint32_t)((uint32_t)~FLASH_AC_LATENCY);
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id_version = (uint8_t)(DBG->ID & 0x00FF);
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if(id_version <= 0x12)
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{
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FLASH->AC |= (uint32_t)((SYSCLK_FREQ - 1) / SYSCLK_FREQ_32M);
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}
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else
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{
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FLASH->AC |= (uint32_t)((SYSCLK_FREQ - 1) / SYSCLK_FREQ_39M);
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}
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/* HCLK = SYSCLK */
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RCC->CFG |= (uint32_t)RCC_CFG_AHBPRES_DIV1;
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/* PCLK2 max 64M */
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if (SYSCLK_FREQ > SYSCLK_FREQ_64M)
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{
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RCC->CFG |= (uint32_t)RCC_CFG_APB2PRES_DIV2;
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}
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else
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{
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RCC->CFG |= (uint32_t)RCC_CFG_APB2PRES_DIV1;
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}
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/* PCLK1 max 32M */
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if (SYSCLK_FREQ > SYSCLK_FREQ_64M)
|
||
{
|
||
RCC->CFG |= (uint32_t)RCC_CFG_APB1PRES_DIV4;
|
||
}
|
||
else if (SYSCLK_FREQ > SYSCLK_FREQ_32M)
|
||
{
|
||
RCC->CFG |= (uint32_t)RCC_CFG_APB1PRES_DIV2;
|
||
}
|
||
else
|
||
{
|
||
RCC->CFG |= (uint32_t)RCC_CFG_APB1PRES_DIV1;
|
||
}
|
||
|
||
#if SYSCLK_SRC == SYSCLK_USE_HSI
|
||
/* Select HSI as system clock source */
|
||
RCC->CFG &= (uint32_t)((uint32_t) ~(RCC_CFG_SCLKSW));
|
||
RCC->CFG |= (uint32_t)RCC_CFG_SCLKSW_HSI;
|
||
|
||
/* Wait till HSI is used as system clock source */
|
||
while ((RCC->CFG & (uint32_t)RCC_CFG_SCLKSTS) != (uint32_t)SYSCLOCK_SRC_HSI)
|
||
{
|
||
}
|
||
#elif SYSCLK_SRC == SYSCLK_USE_HSE
|
||
/* Select HSE as system clock source */
|
||
RCC->CFG &= (uint32_t)((uint32_t) ~(RCC_CFG_SCLKSW));
|
||
RCC->CFG |= (uint32_t)RCC_CFG_SCLKSW_HSE;
|
||
|
||
/* Wait till HSE is used as system clock source */
|
||
while ((RCC->CFG & (uint32_t)RCC_CFG_SCLKSTS) != (uint32_t)SYSCLOCK_SRC_HSE)
|
||
{
|
||
}
|
||
#elif SYSCLK_SRC == SYSCLK_USE_HSI_PLL || SYSCLK_SRC == SYSCLK_USE_HSE_PLL
|
||
PLL_TrimValueLoad();
|
||
/* clear bits */
|
||
RCC->CFG &= (uint32_t)((uint32_t) ~(RCC_CFG_PLLSRC | RCC_CFG_PLLHSEPRES | RCC_CFG_PLLMULFCT));
|
||
RCC->PLLHSIPRE &= (uint32_t)((uint32_t) ~(RCC_PLLHSIPRE_PLLHSIPRE));
|
||
|
||
/* set PLL source */
|
||
temp_value = RCC->CFG;
|
||
temp_value |= (SYSCLK_SRC == SYSCLK_USE_HSI_PLL ? RCC_CFG_PLLSRC_HSI : RCC_CFG_PLLSRC_HSE);
|
||
|
||
#if SYSCLK_SRC == SYSCLK_USE_HSI_PLL
|
||
/* set PLLHSIPRES */
|
||
temp_value1 |= (PLLSRC_DIV == 1 ? RCC_PLLHSIPRE_PLLHSIPRE_HSI : RCC_PLLHSIPRE_PLLHSIPRE_HSI_DIV2);
|
||
#elif SYSCLK_SRC == SYSCLK_USE_HSE_PLL
|
||
/* set PLLHSEPRES */
|
||
temp_value |= (PLLSRC_DIV == 1 ? RCC_CFG_PLLHSEPRES_HSE : RCC_CFG_PLLHSEPRES_HSE_DIV2);
|
||
#endif
|
||
|
||
/* set PLL multiply factor */
|
||
#if PLL_MUL <= PLL_MUL_FACTOR_16
|
||
temp_value |= (PLL_MUL - 2) << RCC_PLLMULFCT_OFFSET;
|
||
#else
|
||
temp_value |= ((PLL_MUL - 17) << RCC_PLLMULFCT_OFFSET) | (1 << 27);
|
||
#endif
|
||
|
||
RCC->CFG = temp_value;
|
||
RCC->PLLHSIPRE = temp_value1;
|
||
|
||
/* Enable PLL */
|
||
RCC->CTRL |= RCC_CTRL_PLLEN;
|
||
|
||
/* Wait till PLL is ready */
|
||
while ((RCC->CTRL & RCC_CTRL_PLLRDF) == RESET)
|
||
{
|
||
}
|
||
|
||
/* Select PLL as system clock source */
|
||
RCC->CFG &= (uint32_t)((uint32_t) ~(RCC_CFG_SCLKSW));
|
||
RCC->CFG |= (uint32_t)RCC_CFG_SCLKSW_PLL;
|
||
|
||
/* Wait till PLL is used as system clock source */
|
||
while ((RCC->CFG & (uint32_t)RCC_CFG_SCLKSTS) != (uint32_t)SYSCLOCK_SRC_PLL)
|
||
{
|
||
}
|
||
#endif
|
||
}
|