mirror of https://gitlab.com/kicad/code/kicad.git
134 lines
4.5 KiB
C++
134 lines
4.5 KiB
C++
/**
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* @brief NETINFO_ITEM class, to handle info on nets: netnames, net constraints
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*/
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/*
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* This program source code file is part of KiCad, a free EDA CAD application.
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*
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* Copyright (C) 2012 Jean-Pierre Charras, jean-pierre.charras@ujf-grenoble.fr
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* Copyright (C) 2012 SoftPLC Corporation, Dick Hollenbeck <dick@softplc.com>
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* Copyright (C) 1992-2012 KiCad Developers, see AUTHORS.txt for contributors.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, you may find one here:
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* http://www.gnu.org/licenses/old-licenses/gpl-2.0.html
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* or you may search the http://www.gnu.org website for the version 2 license,
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* or you may write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
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*/
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#include <pcb_base_frame.h>
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#include <kicad_string.h>
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#include <widgets/msgpanel.h>
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#include <base_units.h>
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#include <board.h>
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#include <track.h>
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/*********************************************************/
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/* class NETINFO_ITEM: handle data relative to a given net */
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/*********************************************************/
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NETINFO_ITEM::NETINFO_ITEM( BOARD* aParent, const wxString& aNetName, int aNetCode ) :
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BOARD_ITEM( aParent, PCB_NETINFO_T ),
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m_netCode( aNetCode ),
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m_netname( aNetName ),
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m_shortNetname( m_netname.AfterLast( '/' ) ),
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m_isCurrent( true )
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{
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m_parent = aParent;
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if( aParent )
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m_netClass = aParent->GetDesignSettings().GetNetClasses().GetDefault();
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else
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m_netClass = std::make_shared<NETCLASS>( "<invalid>" );
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}
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NETINFO_ITEM::~NETINFO_ITEM()
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{
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// m_NetClass is not owned by me.
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}
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void NETINFO_ITEM::SetNetClass( const NETCLASSPTR& aNetClass )
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{
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wxCHECK( m_parent, /* void */ );
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m_netClass = aNetClass ? aNetClass : m_parent->GetDesignSettings().GetNetClasses().GetDefault();
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}
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void NETINFO_ITEM::GetMsgPanelInfo( EDA_DRAW_FRAME* aFrame, std::vector<MSG_PANEL_ITEM>& aList )
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{
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wxString msg;
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aList.emplace_back( _( "Net Name" ), UnescapeString( GetNetname() ) );
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aList.emplace_back( _( "Net Code" ), wxString::Format( "%d", GetNetCode() ) );
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// Warning: for netcode == NETINFO_LIST::ORPHANED, the parent or the board can be NULL
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BOARD * board = m_parent ? m_parent->GetBoard() : NULL;
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if( board )
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{
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int count = 0;
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double lengthNet = 0.0; // This is the length of tracks on pcb
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double lengthPadToDie = 0.0; // this is the length of internal ICs connections
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for( FOOTPRINT* footprint : board->Footprints() )
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{
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for( PAD* pad : footprint->Pads() )
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{
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if( pad->GetNetCode() == GetNetCode() )
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{
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count++;
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lengthPadToDie += pad->GetPadToDieLength();
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}
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}
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}
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aList.emplace_back( _( "Pads" ), wxString::Format( "%d", count ) );
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count = 0;
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for( TRACK* track : board->Tracks() )
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{
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if( track->Type() == PCB_VIA_T )
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{
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if( track->GetNetCode() == GetNetCode() )
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count++;
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}
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if( track->Type() == PCB_TRACE_T )
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{
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if( track->GetNetCode() == GetNetCode() )
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lengthNet += track->GetLength();
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}
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}
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aList.emplace_back( _( "Vias" ), wxString::Format( "%d", count ) );
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// Displays the full net length (tracks on pcb + internal ICs connections ):
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msg = MessageTextFromValue( aFrame->GetUserUnits(), lengthNet + lengthPadToDie );
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aList.emplace_back( _( "Net Length" ), msg );
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// Displays the net length of tracks only:
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msg = MessageTextFromValue( aFrame->GetUserUnits(), lengthNet );
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aList.emplace_back( _( "On Board" ), msg );
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// Displays the net length of internal ICs connections (wires inside ICs):
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msg = MessageTextFromValue( aFrame->GetUserUnits(), lengthPadToDie );
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aList.emplace_back( _( "In Package" ), msg );
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}
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}
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